1. Technical Field
This disclosure relates to processors, and more particularly, to a translation lookaside buffer (TLB) used to store address translations.
2. Description of the Related Art
Modern processors use a structure known as a translation lookaside buffer (TLB) to store virtual-to-physical address translations. When executing a thread, a processor may use virtual addresses to indicate a memory location for data and/or instructions that will be requested by that thread. Each virtual address corresponds to a physical address within the main memory of the system in which the processor is implemented. When a thread executing on a processor needs to access data or instructions stored in memory, it may query the TLB by providing a virtual address. The TLB may then be searched to determine if it currently storing an address translation corresponding to the virtual address. A TLB hit occurs when it is affirmatively determined that the TLB is storing the corresponding translation, based on a match between the provided virtual address and a virtual address stored in the TLB. If the TLB is not storing the requested translation (a TLB miss), then a data structure known as page table may be accessed to determine the address translation.
A TLB typically includes a content addressable memory (CAM) and a random access memory (RAM). Each CAM entry corresponds to one of the RAM entries. Each CAM entry may store a virtual address (and may store other information as well, such as a process ID, etc.). Each RAM entry may store a physical address. When a TLB search is conducted, each CAM entry may be compared to information provided as part of a TLB query. If the comparison determines that the requested virtual address is stored in the CAM, the corresponding entry in the RAM may be read to provide the physical address associated with the virtual address.